Increasing granularity of dirty bit information in hardware assisted memory management systems

ABSTRACT

In a computer system having virtual machines, one or more unused bits of a guest physical address range are allocated for aliasing so that multiple virtually addressed sub-pages can be mapped to a common memory page. When one bit is allocated for aliasing, dirty bit information can be provided at a granularity that is one-half of a memory page. When M bits are allocated for aliasing, dirty bit information can be provided at a granularity that is 1/(2 M )-th of a memory page.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application is a divisional of prior U.S. application Ser. No.13/185,008, filed Jul. 18, 2011, the entire contents of which areincorporated by reference herein.

BACKGROUND

Modern computers employ virtual memory to decouple processes, e.g.,applications running on top of an operating system, from the physicalmemory addresses backing the address space of the processes. Usingvirtual memory enables processes to have a large contiguous addressspace, and allows the computer to run more processes than can fitsimultaneously in their entirety in the available physical memory (i.e.,to “over-commit” memory). To do this, virtual memory space is dividedinto pages of a fixed size (for example, x86 architectures use pagesizes of 4 KB, 2 MB, or 1 GB), and each page of the virtual memory spaceeither maps onto a page within the physical memory of the same page sizeor it maps to nothing. Much of the description in this patent will be interms of x86 architectures. However, a person of skill in the art willunderstand how to apply the teachings of the invention to otherprocessor architectures.

Translation of a virtual memory address to a physical memory address isdone by traversing page tables in memory that contain mappinginformation. To speed up translation, a translation look-aside buffer(TLB) is typically used. The TLB provides faster translation of virtualaddresses to physical addresses than does accessing page tables inmemory because the TLB can provide the beginning-to-end mapping in asingle step, and because the TLB can be implemented in a small (and,therefore, fast to access) data structure closer to or in the CPUitself. However, the TLB is limited in size and it is possible that avirtual memory page cannot be found in the TLB. Whenever this happens, a“TLB miss” occurs, and the mapping has to be performed by a traversal ofthe page tables, commonly known as a “page walk,” a much slower processthan look-ups in the TLB.

In virtualized computer systems, where multiple virtual machines, eachhaving an operating system and applications running therein, can beconfigured to run on a single hardware platform, memory management forthe virtual machines may be carried out by memory management units(MMUs) configured in CPUs that support nested page walks. In suchsystems, a first set of page tables, referred to herein as guest pagetables (gPTs), map the virtual address space of applications running inthe virtual machines, referred to herein as guest virtual address space,to the physical address space that has been emulated for the virtualmachines, referred to herein as guest physical address space.Additionally, a second set of page tables, referred to herein as nestedpage tables (NPTs) (also known as extended page tables), map the guestphysical address space to the address space of machine memory, referredto herein as machine memory address space. Both the first and secondsets of page tables are hierarchically arranged and a pointer to thetop-level, root table for each set of page tables is stored in adistinct register. In x86 architectures that support nested page walks,the register that stores a pointer to the root table of the gPTs isknown as the gCR3 register and the register that stores a pointer to theroot table of the NPTs is known as the nCR3 register. It should berecognized that non-x86 architectures employing guest page tables andnested page tables, or the like, may have different structures andaccessed in a different manner.

FIG. 1 is a schematic diagram that illustrates nested page walks in avirtualized computer system. In the example of FIG. 1, a guest virtualaddress 100 is being mapped by MMU 101 to a machine memory address ofdata 150 stored in machine memory 102 using gPTs 110 and NPTs 120, whichare also stored in machine memory 102. Contents of gPTs 110 at alllevels include pointers, expressed as guest physical addresses, to guestpage tables or guest memory pages, and also permission bits, presentbits, and other control bits, and in some implementations, accessed anddirty bits. Contents of NPTs 120 at all levels include pointers,expressed as machine memory addresses, to nested page tables or machinememory pages and also permission bits, present bits, and other controlbits, and in some implementations, accessed and dirty bits.

The mapping begins with the guest page walker module of MMU 101retrieving a pointer to the root table of gPTs 110 from the gCR3register, which is an address in the guest physical address space. Bits[47:39] of guest virtual address 100 and 3 trailing bits of zeros definethe index into the root table and are copied into the 12 leastsignificant bits of this guest physical address. The resulting guestphysical address, known as the gL4 address, is translated into a machinememory address using the nested page walker module of MMU 101 and NPTs120, and the translated address is used to retrieve an address of thenext lower-level (L3) table, which is also an address in the guestphysical address space. Bits [38:30] of guest virtual address 100 and 3trailing bits of zeros define the index into this L3 table and arecopied into the 12 least significant bits of this guest physicaladdress. The resulting guest physical address, known as the gL3 address,is translated into a machine memory address using the nested page walkermodule of MMU 101 and NPTs 120, and the translated address is used toretrieve an address of the next lower-level (L2) table, which is also anaddress in the guest physical address space. Bits [29:21] of guestvirtual address 100 and 3 trailing bits of zeros define the index intothis L2 table and are copied into the 12 least significant bits of thisguest physical address. The resulting guest physical address, known asthe gL2 address, is translated into a machine memory address using thenested page walker module of MMU 101 and NPTs 120, and the translatedaddress is used to retrieve an address of the next lower-level (L1)table, which is also an address in the guest physical address space.Bits [20:12] of guest virtual address 100 and 3 trailing bits of zerosdefine the index into this L1 table and are copied into the 12 leastsignificant bits of this guest physical address. The resulting guestphysical address, known as the gL1 address, is translated into a machinememory address using the nested page walker module of MMU 101 and NPTs120, and the translated address is used to retrieve an address of a datapage, which is also an address in the guest physical address space. Bits[12:0] of guest virtual address 100 define the index into this data pageand are copied into the 12 least significant bits of this guest physicaladdress. The resulting guest physical address, known as the gPA address,is translated into a machine memory address using the nested page walkermodule of MMU 101 and NPTs 120, and the translated address is used toretrieve the desired content, i.e., data 150.

Bottom-level (L1) tables of gPTs and NPTs have page table entries (PTEs)containing pointers to guest physical or machine memory pages andauxiliary information including an accessed bit (A bit), a dirty bit (Dbit), and various other bits. The A bit, if set to one, indicates thatthe memory page referenced by the entry has been accessed since the Abit was last cleared. The D bit, if set to one, indicates that thememory page referenced by the entry has been modified since the D bitwas last cleared. The dirty bit may be cleared, i.e., set to zero, whenthe contents of the modified memory page are committed to disk.

A bits and D bits are examined by various processes before taking someaction. In a virtualized computer system, D bits of PTEs arecontinuously examined during a process for performing backups and duringa process for migrating the executing state of virtual machines, toidentify those memory pages that have been modified and to transmit tothe backup target machine or the migration target machine only thosememory pages that have been modified. Alternatively, an operation knownas a “diff” operation may be performed on the memory pages that havebeen modified to identify the changed portions of the memory pages, andonly the changed portions are transmitted to the target machine.

When page sizes are relatively large, the efficiency of processes suchas the backup process and the migration process is compromised becauseany modification of a memory page regardless of the size of themodification will cause that memory page to be backed up or migrated.For example, if the memory page size is 4 KB and 8 bytes were written tothat memory page, the entire 4 KB page will need to be backed up ormigrated. It may be possible to build x86 page tables with smallermemory page sizes but this might not be desirable because such a changecould affect memory system performance adversely in other ways or be animplementation burden.

SUMMARY

One or more embodiments of the present invention provide techniques forincreasing the granularity of dirty bit information in a computer systemconfigured with virtual machines, without changing the default memorypage size and with minimal changes to existing memory managementhardware. According to such techniques, one or more unused bits of aguest physical address range are allocated for aliasing so that multiplepage table entries can be mapped to a common memory page. When one bitis allocated for aliasing, dirty bit information can be provided at agranularity that is one-half of a memory page. When two bits areallocated for aliasing, dirty bit information can be provided at agranularity that is one-fourth of a memory page. In general, when N bitsare allocated for aliasing, a granularity of 2^(N) sub-regions of amemory page is achieved.

A data structure according to an embodiment of the present inventionincludes a set of first mapping tables that are hierarchically arrangedand define mappings between guest virtual addresses and guest physicaladdresses, and a set of second mapping tables that are hierarchicallyarranged and define mappings between guest physical addresses andmachine memory addresses. The set of second mapping tables includes aroot table and a plurality of bottom-level tables, wherein each entry ofthe bottom-level tables references a machine memory page in common withat least one other entry of the bottom-level tables, and the at leasttwo entries that reference the machine memory page in common providedifferent indications as to whether the corresponding sub-section of themachine memory page is dirty or not.

A method of mapping virtual addresses to machine memory addresses in acomputer system, according to an embodiment of the present invention,includes the steps of receiving a guest virtual address to be mapped,traversing guest page tables using portions of the guest virtual addressto obtain a guest physical address corresponding to the guest virtualaddress, modifying a binary representation of the guest physical addressby copying the value of a first bit of the binary representation to asecond bit of the binary representation, wherein the second bit is moresignificant than the first bit, and translating the guest physicaladdress to a machine memory address using the modified binaryrepresentation.

A method of backing up a virtual machine, according to an embodiment ofthe present invention, includes the steps of scanning entries of firstand second nested page tables that reference a common machine memorypage, determining that a first section of the common machine memory pageis dirty based on the entry of the first page table that references thecommon machine memory page and determining that a second section of thecommon machine memory page is not dirty based on the entry of the secondpage table that references the common machine memory page, performing anoperation on the first section of the common machine memory page todetermine changes to data stored in the first section of the commonmachine memory page, and transmitting the changes to the data stored inthe first section of the common machine memory page to a backup system.

A method of migrating an executing state of a virtual machine running ina first computer system to a second computer system, according to anembodiment of the present invention includes the steps of scanningentries of first and second nested page tables that reference a commonmachine memory page, determining that a first section of the commonmachine memory page is dirty based on the entry of the first page tablethat references the common machine memory page and determining that asecond section of the common machine memory page is not dirty based onthe entry of the second page table that references the common machinememory page, and transmitting the first section of the common machinememory page to the second computer system.

Further embodiments of the present invention include, withoutlimitation, a non-transitory computer-readable storage medium thatincludes instructions that enable a processing unit to implement one ormore aspects of the above methods as well as a computer systemconfigured to implement one or more aspects of the above methods.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram that illustrates nested page walks in avirtualized computer system.

FIG. 2 depicts a block diagram of a virtualized computer system in whichone or more embodiments of the present invention may be practiced.

FIGS. 3A-3E are schematic diagrams that illustrate nested page walksaccording to one or more embodiments of the present invention.

FIG. 4 is a flow diagram that illustrates the method for mapping virtualaddresses to machine memory pages, according an embodiment of thepresent invention.

FIG. 5 is a flow diagram that illustrates the method for backing up avirtual machine, according an embodiment of the present invention.

FIG. 6 is a flow diagram that illustrates the method for migrating anexecuting state of a virtual machine, according an embodiment of thepresent invention.

DETAILED DESCRIPTION

FIG. 2 depicts a block diagram of a virtualized computer system in whichone or more embodiments of the present invention may be practiced.Virtualized computer system 200 includes multiple virtual machines(VMs), including VM 201, that are running on top of hypervisor 210. EachVM is an abstraction of a physical computer system having virtualhardware resources and a guest operating system that provides guestapplications running in the VM an interface to the virtual hardwareresources. Hypervisor 210 includes a plurality of software layersincluding a kernel that manages hardware resources of hardware platform220 through various drivers (not shown), and virtual machine monitors(VMMs) 211 each emulating hardware resources for a corresponding one ofVMs. Hardware platform 220 includes one or more central processing unit(CPU) 221, machine memory 222, a host bus adapter (HBA) 223 thatconnects virtualized computer system 200 to a persistent storage unitsuch as a disk array, and a network interface card (NIC) 224 thatconnects virtualized computer system 200 to a network. CPU 221 has amemory management unit (MMU) 231 that carries out the mappings from theguest virtual address space to the guest physical address space and fromthe guest physical address space to the machine memory address spaceusing guest page tables (gPTs) 233 and nested page tables (NPTs) 234stored in machine memory 222, or directly from the guest virtual addressspace to the machine memory address space using a translation look-asidebuffer (TLB) 232. It should be recognized that gPTs 233 are maintainedby the guest operating system of a particular VM to provide mapping fromguest virtual address space to guest physical address space, and NPTs234 are maintained by hypervisor 210 to provide mappings from the guestphysical address space to the machine memory address space.

It should be recognized that the various terms, layers andcategorizations used to describe the virtualization components in FIG. 2may be referred to differently without departing from theirfunctionality or the spirit or scope of the invention. One example ofhypervisor 210 that may be used is included as a component of VMware'svSphere product, which is commercially available from VMware, Inc. ofPalo Alto, Calif. (“VMware”). It should further be recognized that othervirtualized computer systems are contemplated, such as hosted virtualmachine systems, where hypervisor 210 is implemented in conjunction withan operating system installed on hardware platform 220.

FIGS. 3A-3E are schematic diagrams that illustrate nested page walksaccording to one or more embodiments of the present invention. Thenested page walks shown in FIGS. 3A-3E are carried out in one or moreembodiments of the present invention when MMU 231 carries out a mappingof a guest virtual address to a machine memory address. Such mappingbegins with the guest page walker module of MMU 231 retrieving a pointerto the root (L4) table of gPTs 233 from the gCR3 register, which is anaddress in the guest physical address space, and copying bits [47:39] ofthe guest virtual address and 3 trailing bits of zeros into the 12 leastsignificant bits of this guest physical address. The resulting guestphysical address, known as the gL4 address, is translated into a machinememory address according to the nested page walk shown in FIG. 3A. Theguest page walker module of MMU 231 then retrieves an address of thenext lower-level (L3) table, which is also an address in the guestphysical address space, using the translated address, and copies bits[38:30] of the guest virtual address and 3 trailing bits of zeros intothe 12 least significant bits of this retrieved address. The resultingguest physical address, known as the gL3 address, is translated into amachine memory address according to the nested page walk shown in FIG.3B. The guest page walker module of MMU 231 then retrieves an address ofthe next lower-level (L2) table, which is also an address in the guestphysical address space, using the translated address, and copies bits[29:21] of the guest virtual address and 3 trailing bits of zeros intothe 12 least significant bits of this retrieved address. The resultingguest physical address, known as the gL2 address, is translated into amachine memory address according to the nested page walk shown in FIG.3C. The guest page walker module of MMU 231 then retrieves an address ofthe next lower-level (L1) table, which is also an address in the guestphysical address space, using the translated address, and copies bits[20:12] of the guest virtual address and 3 trailing bits of zeros intothe 12 least significant bits of this retrieved address. The resultingguest physical address, known as the gL1 address, is translated into amachine memory address according to the nested page walk shown in FIG.3D. The guest page walker module of MMU 231 then retrieves an address ofthe data page, which is also an address in the guest physical addressspace, using the translated address, and copies bits [11:0] of the guestvirtual into the 12 least significant bits of this retrieved address.The resulting guest physical address, known as the gPA address, istranslated into a machine memory address according to the nested pagewalk shown in FIG. 3E, and the desired content is retrieved from thistranslated address.

Page tables depicted in FIGS. 3A-3E are arranged hierarchically. Theyinclude a single root table 321 having entries containing pointers tomultiple second-level tables 322 (including tables 322 a-322 j), eachhaving entries containing pointers to multiple third-level tables 323(including tables 323 a-323 j), each having entries containing pointersto multiple fourth-level or bottom-level page tables 324 (includingtables 324 a-324 j). Entries of bottom-level page tables 324 containpointers 332, 333 (including pointers 332 a, 332 c, 332 e, 332 g, 332 i,333 b, 333 d, 333 f, 333 h, 333 j) to machine memory pages 325 (e.g.,machine memory page 325A-E). These entries also have a D bit (e.g., Dbits 334 a, 334 c, 334 e, 334 g, 334 i, 335 b, 335 d, 335 f, 335 h, 335j), the value of which indicates whether or not the portion of themachine memory page referenced by the entry is dirty. In one embodiment,a D bit value of one indicates that the referenced portion of themachine memory page is dirty and a D bit value of zero indicates thatthe referenced portion of the machine memory page is not dirty. In eachof FIGS. 3A-3E, D bit 334 has a value of 1, indicating that the bottomhalf of the machine memory page 325 referenced by the entry is dirty,and D bit 335 has a value of 0, indicating that the top half of themachine memory page 325 referenced by the entry is not dirty. The MMU(e.g., MMU 231) obtains the location of root table 321 by accessing aregister 320 (e.g., nCR3 register). Then, successive 9-bit segments ofthe binary representation of an address to be translated are used toindex into the page tables at different levels. The 12 least significantbits of the binary representation of the guest physical address are usedas an offset into machine memory page 325. Bits [63:48] are not used inthe mapping in this embodiment as is the convention in memory managementschemes for x86 architectures. However, bits [51:48] are defined asavailable extension bits of a physical address range. It should be clearto a person of skill in the art that an L5 table can be added, withcorresponding extension of the page walks described herein, to enabletranslations of 52-bit guest physical addresses.

The structure of nested page tables shown in FIGS. 3A-3E is the same asconventional page tables. However, before mapping a guest physicaladdress (e.g., gL4 in FIG. 3A, gL3 in FIG. 3B, gL2 in FIG. 3C, gL1 inFIG. 3D, and gPA in FIG. 3E) to a machine memory address, aliasing ofthe bits of the guest physical address is performed, if permitted.Aliasing is permitted in one or more embodiments of the presentinvention if the bit or bits that are being aliased have zero values.

In one embodiment of the present invention, when aliasing is permitted,values of M bits of the guest physical address are respectively copiedinto bits [47:47-(M-1)] of the guest physical address. For example, if Mis two, the values of bits [11:10] from the guest physical address arecopied into bits [47:46]. This copying is performed by MMU 231. Thus,for example, existing x86 processors may be modified to perform thiscopying when performing memory accesses. This copying creates 2^(M)aliased physical address regions within the nested page tables. Thecontents of corresponding entries of bottom-level page tables inmultiple aliased physical address regions are configured to referencethe same machine memory page (e.g., bottom-level page tables 324 i, 324j reference machine memory page 325E in FIG. 3E). If M is one,corresponding entries from two different bottom-level page tablesreference the same machine memory page, the entry from the bottom-levelpage table corresponding to a value of zero at bit [11] being associatedwith the bottom half of the machine memory page and the entry from thebottom-level page table corresponding to a value of one at bit [11]being associated with the top half of the machine memory page. Thus, forexample, referring to FIG. 3E, second-level page table 322 i,third-level page table 323 i and bottom-level page table 324 icorrespond to bit [11] (and therefore also bit [47]) having a value ofzero; while second-level page table 322 j, third-level page table 323 jand bottom-level page table 324 j correspond to bit [11] (and thereforealso bit [47]) having a value of one. As shown in FIG. 3E, the values ofthe D bits of these entries (D bit 334 i and D bit 335 j) may bedifferent. This would happen if, as in the example shown in FIG. 3E, thebottom half of the machine memory page was modified but the top half wasnot. This would also happen if the situation were reversed, where thebottom half of the machine memory page was not modified but the top halfwas. If M is two, corresponding entries from four bottom-level pagetables reference the same machine memory page and each such entry isassociated with a distinct quarter section of the machine memory page.

In the page table data structure illustrated in FIGS. 3A-3E, when M isone, two different guest physical addresses map to the same machinememory page. The difference in the binary representations of these twoguest physical addresses is the modification performed as describedabove that copies the 12-th least significant bit (bit [11]) into a moresignificant bit. More generally, if M is one and machine memory pagesare managed in units of L bytes, the difference in the binaryrepresentations of these two virtual addresses is the modificationperformed as described above that copies the N-th least significant bit,where 2^(N)=L, into a more significant bit.

Embodiments of the present invention described herein employ guest andnested page tables having a 4-level hierarchy and page sizes of 4 KB. Itshould be understood that the present invention is applicable to pagetables having different levels of hierarchy and to different page sizesby monitoring D bits at higher levels in the page table hierarchy.

In an alternative embodiment, a hardware configuration register, whosebits [47:12] can be set or cleared by hypervisor 210, is provided. Foreach bit that is set in this bit vector, the corresponding bit of theguest physical address is claimed as an alias bit. So if M bits are setin this configuration register, there are 2^(M) aliases. The hardwarewill then copy bits [11:11-(M-1)] into the bit positions of the guestphysical address corresponding to the bits that are set in the hardwareconfiguration register, from highest-to-lowest. The bits that are set to1 in the hardware configuration register need not be contiguous.

FIG. 4 is a flow diagram that illustrates the method for mapping guestvirtual addresses to machine page numbers, according an embodiment ofthe present invention. The mapping may be performed to carry out a readoperation or a write operation. In the embodiment illustrated herein,the MMU (e.g., MMU 231) is performing the mapping using TLB (e.g., TLB232) or page tables (e.g., page tables 233, 234). At step 410, the MMUreceives the guest virtual address to be mapped in binary form. Then, atstep 418, the TLB is checked to see if it contains a mapping for themodified guest virtual address, in particular bits [47:12] of themodified guest virtual address. If it does, another check is carried outat step 419 if the operation is a write operation. At step 419, it isdetermined whether the machine page number that the TLB associates withthe guest virtual address is indicated in the TLB as being dirty or not.If it is indicated as being dirty (associated dirty bit value=1), step420 is carried out, where the machine page number that the TLBassociates with the guest virtual address is retrieved from the TLB andthe method terminates. If the machine page number that the TLBassociates with the guest virtual address is not indicated as beingdirty (associated dirty bit value=0), the loop consisting of steps 421through 426 is carried out. The loop consisting of steps 421 through 426is also carried out if a TLB miss is determined at step 418.

The first time through the loop, the guest physical address stored ingCR3 is retrieved at step 421. During subsequent passes through theloop, the guest physical addresses are retrieved from machine memoryaddresses obtained from nested page walks carried out at step 425. Atstep 422, bits [47:47-(M-1)] of the retrieved guest physical address areexamined for zeroes. If they are all zeroes, the loop continues ontostep 424. If one or more of the bits [47:47-(M-1)] are not zero, a pagefault is issued at step 423 and the method terminates. At step 424, bitvalues at bits [11:11-(M-1)] are copied into bits [47:47-(M-1)] toproduce the guest physical address to be used for traversing the nestedpage tables. The nested page tables are traversed at step 425 using theguest physical address produced at step 424 to obtain a machine memoryaddress of the next guest page table to be traversed or the machinememory page corresponding to the guest virtual address to be mapped. If,according to step 426, the guest table page walk is complete (e.g., thepage walk shown in FIG. 3E is carried out at step 425 and the machinememory address of the machine memory page corresponding to the guestvirtual address to be mapped is obtained), bits [47:12] of the machinememory address obtained at step 425 along with the dirty bit value,which will be 1 in the case of a write operation, is added to the TLB atstep 427. The method terminates thereafter. If, according to step 426,the guest table page walk is not complete, e.g., one of the page walksshown in FIGS. 3A-3D is carried out at step 425 and the machine memoryaddress of the next guest page table to be traversed is obtained, theflow returns to step 421.

FIG. 5 is a flow diagram that illustrates the method for backing up avirtual machine, according to an embodiment of the present invention. Inthe embodiment described herein, hypervisor 210 is carrying out thismethod on a periodic basis, and the time interval between backups is setin accordance with a recovery point objective (RCO) that is specified ina backup policy. The backup method described herein may be applied toprovide fault-tolerant, high-availability VMs.

Steps 510 and 512 are carried out to see if the timer that has been setto the backup time interval has lapsed. If the timer has lapsed,hypervisor 210, at step 514, scans all bottom-level nested page tablesfor entries that have the dirty bit set to one. Then, at step 516,hypervisor performs a diff operation on all machine memory page sectionsthat are indicated as being dirty by entries of bottom-level nested pagetables that are dirty. In some cases, the diff operation is alsoperformed on a portion of an adjacent machine memory page section if itis determined that a write operation that caused the machine memory pagesection to be dirtied may have also dirtied (i.e., spilled over to) theadjacent machine memory page section. For example, referring to FIG. 3E,if bottom-level page table 324 a indicates that the bottom half of page325 is dirty via the value of its D bit 334 while bottom-level pagetable 324 b indicates that the top half of page 325 is not dirty via thevalue of its D bit 335, a diff operation is performed on the bottom halfof page 325 and the portion of the top half of page 325 adjacent to thebottom half of page 325 that could have been dirtied as a result of awrite operation that began on the bottom half of page 325 and spilledinto the top half of page 325. In one embodiment, where the maximum sizeof a single write operation is 16 or N bytes, the portion of theadjacent machine memory page section that also undergoes a diffoperation is 15 or (N−1) bytes. At step 518, changes to machine memorypage sections as determined through the diff operation are transmittedto a backup machine. Then, at step 520, the timer is reset, and themethod returns to step 510.

In the embodiment of the present invention described above, the diffoperation is used to minimize the amount of data being transmitted overthe network. It should be recognized that other operations that reducenetwork bandwidth consumption, such as compression and precopy, may beemployed in place of the diff operation.

FIG. 6 is a flow diagram that illustrates the method for migrating anexecuting state of a virtual machine (VM), according to an embodiment ofthe present invention. In the embodiment described herein, hypervisor210 is carrying out this method and, in doing so, transmits all machinememory pages of the VM to a destination server over a network. As a wayto reduce the downtime of the VM, the VM is stunned and executioncontrol is switched over to the destination server only when the totalsize of the machine memory pages left to be transmitted to thedestination server is below a certain threshold. In addition, nestedpage tables referenced below correspond to nested page tables beingmaintained by hypervisor 210 for the VM that is being migrated.

At step 610, all machine memory pages of the VM are transmitted to thedestination server. While this is happening, the VM continues to run andsome of these machine memory pages become dirtied and D bits in theentries of bottom-level nested page tables corresponding to thesemachine memory pages will be set to one. At step 612, bottom-levelnested page tables are scanned for entries that have the dirty bit setto one. Then, at step 614, the total size of data to be transmitted tothe destination server is computed and compared against a threshold. Thedata to be transmitted includes machine memory page sections referencedby entries in bottom-level nested page tables that have the D bit set toone. In some cases, the data to be transmitted includes a portion of anadjacent machine memory page section if it is determined that a writeoperation that caused the machine memory page section to be dirtied mayhave also dirtied the adjacent machine memory page section. If the totalsize computed at step 614 is not less than the threshold, all dirtymachine memory page sections referenced by entries in bottom-levelnested page tables and any portions of adjacent machine memory pagesections that could have been dirtied are transmitted to the destinationserver. The method then returns to step 612 to identify machine memorypage sections that may have become dirtied while step 615 was beingcarried out.

Returning to the decision block at step 614, if the total size computedat step 614 is less than the threshold, the VM is stunned at step 616and, at step 618, all dirty machine memory page sections referenced byentries in bottom-level nested page tables and any portions of adjacentmachine memory page sections that could have been dirtied aretransmitted to the destination server. After step 618, the methodterminates, and hypervisor 210 can hand over execution control of the VMto the destination server.

Alternative embodiments of the present invention include a backup methodwhere the diff operation is not performed and entire machine memory pagesections are transmitted to the backup machine, and a migration methodwhere the diff operation is performed and only the changed parts ofmachine memory page sections are transmitted to the destination serverIn the examples given above, more granular dirty bit informationprovides savings in computational power in the case where diffoperations are performed and only the changed portions are transmittedover the network to the target machine, and provides savings in networkbandwidth consumption in the case where diff operations are notperformed and machine memory page sections in their entirety aretransmitted over the network to the target machine.

In a further embodiment of the present invention, the conventionalcomponent of the MMU that handles write operations that span more thanone machine memory page is modified to also handle write operations thatspan more than one machine memory page section within a single machinememory page. With this modification, a write operation that spans morethan one machine memory page section within a single machine memory pageis translated into two separate write operations or two separate TLB andMMU interactions, each of which is confined to a single machine memorypage section. As a result, a write operation that dirties a machinememory page section and spills over to another machine memory pagesection across a page section boundary to dirty the adjacent machinememory page section is translated into two separate write operationsthat cause the dirty bits in the PTEs that reference these two machinememory page sections to be set to 1. In addition, when checking to seeif a write operation spans more than one machine memory page sectionwithin a single machine memory page, only the first and last bytes ofthe write operation are checked. It should be recognized that checkingthe first and last bytes in this manner is valid because writeoperations are strictly smaller than a page size.

It should be recognized that an additional benefit of the embodiments ofthe present invention described herein is that accessed bits acquire thesame improvement in granularity that the dirty bits gain. Therefore,further embodiments of the present invention contemplate the use of themore granular accessed bit information in various applications in waysthat would be evident to persons of skill in the art.

The various embodiments described herein may employ variouscomputer-implemented operations involving data stored in computersystems. For example, these operations may require physical manipulationof physical quantities which usually, though not necessarily, take theform of electrical or magnetic signals where they, or representations ofthem, are capable of being stored, transferred, combined, compared, orotherwise manipulated. Further, such manipulations are often referred toin terms, such as producing, identifying, determining, or comparing. Anyoperations described herein that form part of one or more embodiments ofthe invention may be useful machine operations. In addition, one or moreembodiments of the invention also relate to a device or an apparatus forperforming these operations. The apparatus may be specially constructedfor specific required purposes, or it may be a general purpose computerselectively activated or configured by a computer program stored in thecomputer. In particular, various general purpose machines may be usedwith computer programs written in accordance with the descriptionprovided herein, or it may be more convenient to construct a morespecialized apparatus to perform the required operations.

The various embodiments described herein may be practiced with othercomputer system configurations including hand-held devices,microprocessor systems, microprocessor-based or programmable consumerelectronics, minicomputers, mainframe computers, and the like.

One or more embodiments of the present invention may be implemented asone or more computer programs or as one or more computer program modulesembodied in one or more computer readable media. The term computerreadable medium refers to any data storage device that can store datawhich can thereafter be input to a computer system; computer readablemedia may be based on any existing or subsequently developed technologyfor embodying computer programs in a manner that enables them to be readby a computer. Examples of a computer readable medium include a harddrive, network attached storage (NAS), read-only memory, random-accessmemory (e.g., a flash memory device), a CD-ROM (Compact Disc-ROM), aCD-R, or a CD-RW, a DVD (Digital Versatile Disc), a magnetic tape, andother optical and non-optical data storage devices. The computerreadable medium can also be distributed over a network coupled computersystem so that the computer readable code is stored and executed in adistributed fashion.

Although one or more embodiments of the present invention have beendescribed in some detail for clarity of understanding, it will beapparent that certain changes and modifications may be made within thescope of the claims. Accordingly, the described embodiments are to beconsidered as illustrative and not restrictive, and the scope of theclaims is not to be limited to details given herein, but may be modifiedwithin the scope and equivalents of the claims. In the claims, elementsand/or steps do not imply any particular order of operation, unlessexplicitly stated in the claims.

Plural instances may be provided for components, operations orstructures described herein as a single instance. Finally, boundariesbetween various components, operations and data stores are somewhatarbitrary, and particular operations are illustrated in the context ofspecific illustrative configurations. Other allocations of functionalityare envisioned and may fall within the scope of the invention(s). Ingeneral, structures and functionality presented as separate componentsin exemplary configurations may be implemented as a combined structureor component. Similarly, structures and functionality presented as asingle component may be implemented as separate components. These andother variations, modifications, additions, and improvements may fallwithin the scope of the appended claims(s).

What is claimed is:
 1. A data structure used by a memory management unit(MMU) of a computer system having virtual machines instantiated therein,wherein the MMU is configured to execute a first mapping from a guestvirtual address space to a guest physical address space and a secondmapping from the guest physical address space to a machine memoryaddress space, the data structure comprising: a set of first mappingtables that are hierarchically arranged and define mappings betweenguest virtual addresses and guest physical addresses; and a set ofsecond mapping tables that are hierarchically arranged and definemappings between guest physical addresses and machine memory addresses,the set of second mapping tables including a root table and a pluralityof bottom-level tables, wherein each of a plurality of entries of thebottom-level tables references a machine memory page in common with atleast one other entry of the bottom-level tables, and each of theplurality of entries of the bottom-level tables includes a status bitvalue that indicates whether or not data stored in the machine memorypage referenced by said entry is dirty or not, and said status bitvalues of at least two entries of the bottom-level tables that referencethe same machine memory page are different.
 2. The data structure ofclaim 1, wherein said at least two entries of the bottom-level tablesthat reference the same machine memory page are associated with at leasttwo different guest physical addresses.
 3. The data structure of claim2, wherein the two different guest physical addresses that reference thesame memory page include a first guest physical address that referencesone of the first mapping tables and a second guest physical address thatdiffers from the first guest physical address by at least one bit value.4. The data structure of claim 3, wherein the first guest physicaladdress references a root table of the first mapping tables.
 5. The datastructure of claim 3, wherein the first guest physical addressreferences an intermediate-level table of the first mapping tables. 6.The data structure of claim 3, wherein the first guest physical addressreferences a bottom-level table of the first mapping tables.
 7. The datastructure of claim 2, wherein the two different guest physical addressesthat reference the same memory page include a first guest physicaladdress that references a page of data and a second guest physicaladdress that differs from the first guest physical address by at leastone bit value.
 8. A method of mapping guest virtual addresses to machinememory addresses in a computer system having virtual machinesinstantiated therein, comprising: receiving a guest virtual address tobe mapped; traversing guest page tables using portions of the guestvirtual address to obtain a guest physical address corresponding to theguest virtual address; modifying a binary representation of the guestphysical address corresponding to the guest virtual address by copyingthe value of a first bit of the binary representation to a second bit ofthe binary representation, wherein the second bit is more significantthan the first bit; and translating the guest physical addresscorresponding to the guest virtual address to a machine memory addressusing the modified binary representation.
 9. The method of claim 8,wherein the guest physical address is translated to the machine memoryaddress using nested page tables.
 10. The method of claim 8, whereinsaid traversing includes: generating a guest physical addresscorresponding to one of the guest page tables; modifying a binaryrepresentation of the guest physical address corresponding to one of theguest page tables by copying the value of a first bit of the binaryrepresentation to a second bit of the binary representation, wherein thesecond bit is more significant than the first bit; and traversing thenested page tables to translate the guest physical address correspondingto one of the guest page tables to a machine memory address.
 11. Themethod of claim 10, wherein bit positions of the first and second bitsin the modified binary representation of the guest physical addresscorresponding to the guest virtual address are the same as bit positionsof the first and second bits in the modified binary representation ofthe guest physical address corresponding to one of the guest pagetables.
 12. The method of claim 8, wherein the binary representation ofthe guest physical address corresponding to the guest virtual address isfurther modified by copying the value of one or more additional bits ofthe binary representation to one or more additional bits of the binaryrepresentation that are more significant.
 13. The method of claim 8,further comprising: prior to said modifying, verifying that the secondbit has a value of zero.
 14. The method of claim 8, further comprising:adding a mapping of the guest virtual address to the machine memoryaddress as an entry to a translation lookaside buffer.
 15. A method ofmigrating an executing state of a virtual machine running in a firstcomputer system to a second computer system, the first and secondcomputer systems each having a memory management unit (MMU) thatexecutes a first mapping from a guest virtual address space to a guestphysical address space and a second mapping from the guest physicaladdress space to a machine memory address space using the data structureof claim 1, said method comprising: scanning entries of first and secondpage tables in the set of second mapping tables that reference a commonmachine memory page; determining that a first section of the commonmachine memory page is dirty based on the entry of the first page tablethat references the common machine memory page and determining that asecond section of the common machine memory page is not dirty based onthe entry of the second page table that references the common machinememory page; and transmitting the first section of the common machinememory page to the second computer system.
 16. The method of claim 15,further comprising: stunning the virtual machine; and transmitting allsections of machine memory pages that are dirty to the second computersystem.
 17. The method of claim 15, wherein the first and secondsections of the common machine memory page do not overlap and each has asize that is 1/(2^(M)) of the size of the common machine memory page,where M is an integer greater than or equal to 1.